CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs

Author

Zarandi, Hamid R. ; Miremadi, Seyed G. ; Pradhan, Dhiraj K. ; Mathew, Jimson

Author_Institution

Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran

fYear

2007

fDate

27-30 May 2007

Firstpage

3675

Lastpage

3678

Abstract

This paper presents a SEU-mitigative placement and route of circuits in the FPGAs which is based on the popular placement and route tool. The tool is modified so that during placement and routing, decisions are taken with awareness of SEU-mitigation and no redundancies during the placement and routing are used but the algorithms are based on the SEU avoidance. We have investigated the effect of this tool on several MCNC benchmarks and the results of the placement and routing have been compared to the traditional one. The evaluations of results show that placement and routing can decrease the SEU rate of circuits implemented on FPGAs about 22%. However, it increases critical path delay and power consumptions of the circuits.

Keywords

fault tolerant computing; field programmable gate arrays; network routing; CAD-directed SEU susceptibility reduction; FPGA circuits designs; placement and route tool; Circuit synthesis; Delay estimation; Digital systems; Energy consumption; Field programmable gate arrays; Packaging; Programmable logic arrays; Routing; Single event upset; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Conference_Location

New Orleans, LA

Print_ISBN

1-4244-0920-9

Electronic_ISBN

1-4244-0921-7

Type

conf

DOI

10.1109/ISCAS.2007.378640

Filename

4253478