DocumentCode
465187
Title
1-V Linear CMOS Transconductor with -65 dB THD in Nano-Scale CMOS Technology
Author
Lo, Tien-Yu ; Hung, Chung-Chih
Author_Institution
Dept. of Commun. Eng., National Chiao Tung Univ., Hsinchu
fYear
2007
fDate
27-30 May 2007
Firstpage
3792
Lastpage
3795
Abstract
This paper presents a high linearity MOSFET-only transconductor based on differential structures. The linearity is improved by mobility compensation techniques as the device size is scaled down in the nano-scale CMOS technology. Transconductance tuning could be achieved by transistors operating in the linear region. The simulated total harmonic distortion (THD) under 1-V power supply voltage shows 12 dB improvement of the proposed version, and -65 dB THD can be achieved for a 1 MHz 700 mVpp differential input. Monte-Carlo simulation over the corner variation and transistor mismatch guarantees the shown performance. The static power consumption is 130 muW. Simulation results demonstrate the agreement with theoretical analyses.
Keywords
CMOS analogue integrated circuits; Monte Carlo methods; circuit tuning; harmonic distortion; nanotechnology; 1 V; 130 muW; MOSFET-only transconductor; Monte-Carlo simulation; THD; linear CMOS transconductor; mobility compensation techniques; nanoscale CMOS technology; static power consumption; total harmonic distortion; transconductance tuning; CMOS technology; Energy consumption; Linearity; MOSFETs; Nanoscale devices; Power supplies; Total harmonic distortion; Transconductance; Transconductors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location
New Orleans, LA
Print_ISBN
1-4244-0920-9
Electronic_ISBN
1-4244-0921-7
Type
conf
DOI
10.1109/ISCAS.2007.378787
Filename
4253507
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