Design of the Basic Building Block of a High-Speed Flexible and Modular Pipelined ADC

This paper presents the design procedure and performance of the basic building block of a flexible/modular pipelined ADC. We report the advantages of adopting a flexible ADC approach (Zanikopoulos et al., 2005) and we comment on the performance range that can be covered by this. Targeting a sampling frequency range from 50MS/s to 500MS/s and an accuracy range from 8b to 12b, we present and justify our design decisions leading to the implementation of the adjustable basic building block. The principle idea is the use of circuitries that can fully benefit from the speed-power consumption trade-off, while maintaining the desired accuracy. We employ dynamic circuitry and furthermore propose a fully adjustable open-loop amplifier suitable for flexible ADC realizations. Finally, we present the accuracy results and power consumption estimations along with the size of the building block implemented in a CMOS 0.18mum technology.