DocumentCode
465214
Title
Tiled Interleaving for Multi-Level 2-D Discrete Wavelet Transform
Author
Kim, Jung-Wook ; Song, Jinook ; Lee, Seokho ; Park, In-Cheol
Author_Institution
Digital Printing Div., Samsung Electron., Suwon
fYear
2007
fDate
27-30 May 2007
Firstpage
3984
Lastpage
3987
Abstract
This paper presents a new architecture of 2D discrete wavelet transform (DWT) proposed for JPEG 2000. In the proposed architecture, the image is segmented into tiles each of which is sequentially processed to minimize the size of buffers required to process 2D DWT, and multi-level DWTs are interleaved to reduce the size of the repeat buffer drastically. Compared to the conventional architecture, the overall memory size is reduced by 85% and 92% for 256 times 256 and 512 times 512 images, respectively. The proposed DWT processor needs only 5kB memory for 256 times 256 images, and operates at 250MHz in 0.25-mu technology.
Keywords
discrete wavelet transforms; image segmentation; interleaved codes; 0.25 micron; 250 MHz; multilevel 2D discrete wavelet transform; tiled interleaving; Digital printing; Discrete cosine transforms; Discrete wavelet transforms; Image coding; Interleaved codes; Low pass filters; Pipelines; Pixel; Process design; Transform coding;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location
New Orleans, LA
Print_ISBN
1-4244-0920-9
Electronic_ISBN
1-4244-0921-7
Type
conf
DOI
10.1109/ISCAS.2007.378673
Filename
4253555
Link To Document