Statistical Analysis of Full-Chip Leakage Power Considering Junction Tunneling Leakage

In this paper we address the the growing issue of junction tunneling leakage (I_junc) at the circuit level. Specifically, we develop a fast approach to analyze the state-dependent total leakage power of a large circuit block, considering I_junc, sub-threshold leakage (I_sub), and gate oxide leakage (I_gate). We then propose our algorithm to estimate the full-chip leakage power with consideration of both Gaussian and non- Gaussian parameter distributions, capturing spatial correlations using a grid-based model. Experiments on ISCAS85 benchmarks demonstrate that the estimated results are very accurate and efficient. For a circuit with G gates, the complexity of our approach is O(G).