On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise

Decap allocation are the primary methods for addressing the dynamic voltage, noise problem of on-chip power networks. When space in the immediate proximity of a hot, spot is constrained, simply adding decoupling capacitance without improving the local wiring is ineffective. Based on this key observation, we propose an efficient co-optimization of decap allocation and local wiring enhancement. The method solves a linear program (LP) iteratively and is based on the decap budgeting algorithm [10], Experimental results on two actual chip designs demonstrate the area and run-lime, efficiency of the co -optimization algorithm. Moreover, it provides excellent solutions even in cases where decap allocation alone fails to provide a feasible, solution.