DocumentCode
465290
Title
Chip Multi-Processor Generator
Author
Solomatnikov, Alex ; Firoozshahian, Amin ; Qadeer, Wajahat ; Shacham, Ofer ; Kelley, Kyle ; Asgar, Zain ; Wachs, Megan ; Hameed, Rehan ; Horowitz, Mark
Author_Institution
Stanford Univ., Stanford
fYear
2007
fDate
4-8 June 2007
Firstpage
262
Lastpage
263
Abstract
The drive for low-power, high performance computation coupled with the extremely high design costs for ASIC designs, has driven a number of designers to try to create a flexible, universal computing platform that will supersede the microprocessor. We argue that these flexible, general computing chips are trying to accomplish more than is commercially needed. Since design NRE costs are an order of magnitude larger than fabrication NRE costs, a two-step design system seems attractive. First, the users configure/program a flexible computing framework to run their application with the desired performance. Then, the system "compiles" the program and configuration, tailoring the original framework to create a chip that is optimized toward the desired set of applications. Thus the user gets the reduced development costs of using a flexible solution with the efficiency of a custom chip.
Keywords
logic design; microprocessor chips; ASIC design; application specific integrated circuits; chip multiprocessor generator; nonrecurring engineering; Algorithm design and analysis; Application specific integrated circuits; CMOS technology; Cost function; Design optimization; Fabrication; Hardware; High performance computing; Microprocessors; Permission; Algorithms; Chip Multi-Processor; Design; High-Level Design; Performance;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE
Conference_Location
San Diego, CA
ISSN
0738-100X
Print_ISBN
978-1-59593-627-1
Type
conf
Filename
4261183
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