DocumentCode
465305
Title
Enhancing FPGA Performance for Arithmetic Circuits
Author
Brisk, Philip ; Verma, Ajay K. ; Ienne, Paolo ; Parandeh-Afshar, Hadi
Author_Institution
Swiss Fed. Inst. of Technol. (EPFL), Lausanne
fYear
2007
fDate
4-8 June 2007
Firstpage
334
Lastpage
337
Abstract
FPGAs offer flexibility and cost-effectiveness that ASICs cannot match; however, their performance is quite poor in comparison, especially for arithmetic dominated circuits. To address this issue, this paper introduces a novel reconfigurable lattice built from counters rather than look-up tables that can effectively accelerate the arithmetic portions of a circuit. We intend to integrate this novel lattice onto the same die as an FPGA.
Keywords
digital arithmetic; field programmable gate arrays; FPGA; arithmetic circuits; field programmable gate arrays; reconfigurable lattice; Acceleration; Adders; Application specific integrated circuits; Arithmetic; Counting circuits; Field programmable gate arrays; Lattices; Permission; Programmable logic arrays; Table lookup; Algorithms; Compressor Tree; Design; Field Programmable Counter Array (FPCA) Look-up Table (LUT); Field Programmable Gate Array (FPGA); Performance;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE
Conference_Location
San Diego, CA
ISSN
0738-100X
Print_ISBN
978-1-59593-627-1
Type
conf
Filename
4261201
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