Title :
Design-Silicon Timing Correlation A Data Mining Perspective
Author :
Wang, Li.-C. ; Bastani, Pouria ; Abadir, Magdy S.
Abstract :
In the post-silicon stage, timing information can be extracted from two sources: (1) on-chip monitors and (2) delay testing. In the past, delay test data has been overlooked in the correlation study. In this paper, we take path delay testing as an example to illustrate how test data can be incorporated in the overall design-silicon correlation effort. We describe a path-based methodology that correlates measured path delays from the good chips, to the path delays predicted by timing analysis. We discuss how statistical data mining can be employed for extracting information and show experimental results to demonstrate the potential of the proposed methodology.
Keywords :
circuit CAD; correlation methods; monolithic integrated circuits; timing; design-silicon timing correlation; on-chip monitors; path delay testing; statistical data mining; Data mining; Delay; Design methodology; Failure analysis; Hardware; Semiconductor device measurement; Semiconductor device testing; Silicon; Timing; Uncertainty; Algorithms; Correlation; Learning; Performance and Reliability; Statistical Timing; Test; Timing;
Conference_Titel :
Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-59593-627-1