DocumentCode :
465317
Title :
Characterizing Process Variation in Nanometer CMOS
Author :
Agarwal, Kanak ; Nassif, Sani
Author_Institution :
IBM Corp., Austin
fYear :
2007
fDate :
4-8 June 2007
Firstpage :
396
Lastpage :
399
Abstract :
The correlation of a statistical analysis tool to hardware depends on the accuracy of underlying variation models. The models should represent actual process behavior as measured in silicon. In this paper, we present an overview of test structures for characterizing statistical variation of process parameters. We discuss the test structure design and characterization strategy for calibrating random and layout dependent systematic components of process variation. We also show measurement results from several fabricated structures in 65-nm CMOS technologies.
Keywords :
CMOS integrated circuits; nanotechnology; statistical analysis; layout dependent systematic components; nanometer CMOS; process variation; silicon; statistical analysis tool; statistical variation; test structure design; variation models; CMOS process; CMOS technology; Circuit testing; FETs; Fluctuations; Integrated circuit measurements; Integrated circuit modeling; Semiconductor device modeling; Silicon; System testing; Characterization; Design; Measurement; Modeling; Performance; Reliability; Test structure; Variation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE
Conference_Location :
San Diego, CA
ISSN :
0738-100X
Print_ISBN :
978-1-59593-627-1
Type :
conf
Filename :
4261214
Link To Document :
بازگشت