DocumentCode
465351
Title
On-The-Fly Resolve Trace Minimization
Author
Shacham, Ohad ; Yorav, Karen
Author_Institution
IBM, Haifa
fYear
2007
fDate
4-8 June 2007
Firstpage
594
Lastpage
599
Abstract
The ability of modern SAT solvers to produce proofs of un- satisfiability for Boolean formulas has become a powerful tool for EDA applications. Proofs are generated from a resolve trace that captures information about the creation of all conflict clauses. Due to their sizes, resolve traces are kept in files. The sizes of these files makes the use of proofs of un- satisfiability impractical for industrial tools. Although only a small part of the resolve trace is eventually used, until now it was not known how to filter out unnecessary information. We propose a simple algorithm for on-the-fly resolve trace minimization in which we identify clauses that are guaranteed not to take part in the proof of unsatisfiability, and delete all of their associated information. This algorithm dramatically decreases the size of the resolve trace, to the point where it can be stored in the main memory. Our experiments reveal that the minimized trace is typically 3 to 6 times smaller. This makes the use of proofs of unsatisfiability and the computation of unsat cores more practical and will enable future applications to take advantage of it.
Keywords
computability; formal verification; theorem proving; Boolean formula; SAT solver; on-the-fly resolve trace minimization; unsatisfiability; Artificial intelligence; Electronic design automation and methodology; Formal verification; Information filtering; Information filters; Laboratories; Logic design; Minimization methods; Performance analysis; Permission; SAT solvers; SAT-based verification; Verification; unsatisfiable core;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE
Conference_Location
San Diego, CA
ISSN
0738-100X
Print_ISBN
978-1-59593-627-1
Type
conf
Filename
4261252
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