A DFT Method for Time Expansion Model at Register Transfer Level

This paper presents a non-scan design-for-testability method for register transfer level circuits. We first introduce a new testability of RTL circuits called partially strong testability. The partially strong testability guarantees that the number of time frames required for any testable fault is bounded by a linear function of the number of registers in the RTL circuit during test generation process. We also propose a DFT method to make RTL circuits partially strongly testable. Experimental results show that we can reduce hardware overhead and test application time drastically compared to the previous methods. Moreover, the proposed method can achieve 100% fault efficiency in practical test generation time and allow at-speed testing.