Title :
The KILL Rule for Multicore
Author :
Agarwal, Anant ; Levy, Markus
Author_Institution :
MIT, Cambridge
Abstract :
Multicore has shown significant performance and power advantages over single cores in commercial systems with a 2-4 cores. Applying a corollary of Moore\´s Law for multicore, we expect to see 1K multicore chips within a decade. 1K multicore systems introduce significant architectural challenges. One of these is the power efficiency challenge. Today\´s cores consume 10\´s of watts. Even at about one watt per core, a 1K-core chip would need to dissipate 1K watts! This paper discusses the "Kill rule for multicore" for power-efficient multicore design, an approach inspired by the "Kiss rule for RISC processor design". Kill stands for Kill if less than linear, and represents a design approach in which any additional area allocated to a resource within a core, such as a cache, is carefully traded off against using the area for additional cores. The Kill rule states that we must increase resource size (for example, cache size) only if for every 1% increase in core area there is at least a 1% increase in core performance.
Keywords :
microprocessor chips; KILL rule; multicore chips; power-efficient multicore design; Computer applications; Computer architecture; Engines; Moore´s Law; Multicore processing; Parallel processing; Permission; Process design; Reduced instruction set computing; Resource management; CMP; Design; Economics; Experimentation; Kill Rule; Measurement; Performance; Theory; computer architecture; core; multicore; parallel computing; power efficiency; stream processing; tiled multicore;
Conference_Titel :
Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-59593-627-1