• DocumentCode
    465382
  • Title

    Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture

  • Author

    Lim, Kyoung-Hwan ; Kim, Yonghwan ; Kim, Taewhan

  • Author_Institution
    Seoul Nat. Univ., Seoul
  • fYear
    2007
  • fDate
    4-8 June 2007
  • Firstpage
    765
  • Lastpage
    770
  • Abstract
    Distributed register-file microarchitecture (DRFM) which comprises multiple uniform blocks (called islands), each containing a dedicated register file, functional unit(s) and data- routing logic, has been known as a very attractive architecture for implementing designs with platform-featured on- chip memory or register-file IP blocks. In comparison with the discrete-register based architecture, DRFM offers a higher degree of opportunity of reducing the cost of global (inter- island) connections by confining as many the computations to the inside of the islands as possible. Consequently, for DRFM architecture, two important problems to be solved effectively in high-level synthesis are: (problem 1) scheduling and resource binding for minimizing inter-island connections, and (problem 2) data transfer (i.e., communication) scheduling through the inter-island connections for minimizing the access conflicts among the data transfers. This work proposes novel solutions to the two problems. Specifically, for problem 1 previous work solves it in two separate steps: (i) scheduling and (ii) then determining the inter-island connections by resource binding to islands. However, in our algorithm called DFRM-int, we place primary importance on the cost of interconnections. Consequently, we minimize the cost of interconnections first to fully exploit the effects of scheduling on interconnect and then to schedule the operations later. For problem 2, previous work tries to solve the access conflicts by forwarding data directly to the destination island. However, in our algorithm called DFRM-com, we devise an efficient technique of exploring an extensive design space of data forwarding indirectly as well as directly to find a near-optimal solution. By applying our proposed synthesis approach DFRM-int+DFRM-com we are able to reduce the inter-island connections by 18.1% more, compared to that by the DRFM approach in [4], even completely eliminating register-file access conflicts, which c- ould never been resolved by [4], without any latency increase.
  • Keywords
    distributed databases; network operating systems; data transfer; distributed register-file microarchitecture; interconnect-communication synthesis; multiple uniform blocks; Algorithm design and analysis; Computer architecture; Costs; Delay; High level synthesis; Logic design; Microarchitecture; Processor scheduling; Registers; Routing; Algorithms; Design; Synthesis; communication; distributed register file;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE
  • Conference_Location
    San Diego, CA
  • ISSN
    0738-100X
  • Print_ISBN
    978-1-59593-627-1
  • Type

    conf

  • Filename
    4261286