How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs

One unique property of an FPGA chip is that any logic perturbation inside its Look-Up-Tables (LUTs) is totally area/delay-free. Amongst others, this free LUT-internal resource perturbation can also be used to trade for critical LUT-external logic/wire removals for EDA improvements, an extra flexibility ignored before. Using rewiring technique for such logic perturbations, we show that significant cut-downs upon already excellent results from the state-of-the-art DAOmap mappings and the TVPR place-and-route can still be obtained. This logic perturbation operation can further reduce the number of LUTs by up to 33.7% (avg. 10%) without delay penalty and also reduce critical path delay by up to 31.7% (avg. 11%) without disturbing placement or sacrificing area in the final routing. For delay reduction, under proper rewiring strategy, the CPU time used by rewiring is only 5% of the total run time consumed by TVPR´s placement and routing. This idea of perturbing logic between the free LUT-internal and critical LUT-external circuit resources is simple and proved to be powerful. The encouraging results suggest a new technique for an optimization domain less explored for FPGA design flow.