DocumentCode
465412
Title
Clock Period Minimization with Minimum Delay Insertion
Author
Huang, Shih-Hsu ; Cheng, Chun-Hua ; Chang, Chia-Ming ; Nieh, Yow-Tyng
Author_Institution
Chung Yuan Christian Univ., Chung Li
fYear
2007
fDate
4-8 June 2007
Firstpage
970
Lastpage
975
Abstract
The combination of clock skew scheduling and delay insertion may lead to further clock period reduction. Although some previous works can minimize the clock period, they only heuristically reduce the required inserted delay. However, since the delay insertion is an ECO (engineering change order) process, minimizing the required inserted delay is very important for the design closure, hi this paper, we present a linear program to formally formulate the simultaneous application of clock skew scheduling and delay insertion. Our objective is not only to achieve the lower bound of the clock period, but also to achieve the lower bound of required inserted delay. Compared with previous works, our paper has the following two significant contributions: (1) our approach is the first work that guarantees solving this problem optimally; and (2) our paper is the first proof of showing that the time complexity of this problem is polynomial.
Keywords
circuit optimisation; clocks; delays; linear programming; scheduling; clock period minimization; clock skew scheduling; engineering change order process; linear program; minimum delay insertion; Clocks; Delay; Design engineering; Design optimization; Libraries; Logic design; Polynomials; Scheduling algorithm; Timing; Upper bound; Algorithms; High performance; Performance; Sequential circuits; Timing optimization;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE
Conference_Location
San Diego, CA
ISSN
0738-100X
Print_ISBN
978-1-59593-627-1
Type
conf
Filename
4261325
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