A Fully-Automated Desynchronization Flow for Synchronous Circuits

Variability is one of the fundamental problems faced by nano-scale electronic circuits and is expected to become even worse as process technology scales. Desynchronization is a design methodology, which converts a synchronous gate- level circuit into a more robust asynchronous one. In this paper, we describe the first fully-automated desynchronization design flow, based only on contemporary synchronous EDA tools and a new point tool for performing the desynchronization transformation. The flow was used to implement, down to mask layout level, a simple pipelined processor in a 90 nm industrial library. We show that the desynchronization methodology can be easily integrated into contemporary industrial EDA flows. Results, on the design implemented, indicate that desynchronized circuits exhibit increased variability tolerance and better average case performance, for a small area and power overhead.