Design and Synthesis of Flagged Binary Adders with Constant Addition

Multi-operand addition is utilized in various applications like, multiplication, convolution and several image processing algorithms such as filtering. Various adder architectures have been proposed to accomplish the addition of more than two operands, consuming minimum delay and area. Recently, a new technique called flagged prefix addition has been proposed that utilizes prefix tree adders to perform increment and decrement operations by generating flag bits. An extension to this adder has also been proposed enhancing the functionality of the same to allow the addition of any arbitrary number, thereby accomplishing multi-operand addition. This paper extends the idea of generating the flag bits to the carry-skip and the carry-select adders. A thorough evaluation has been performed to analyze the performance of the carry-select, carry-skip, and the prefix tree architectures incorporating the new design in terms of power, area, and delay.