An Ultra-Low Voltage 200 MHz 0.6 pJ Add-Compare-Select Unit in 180 nm CMOS

A high-performance ultra-low voltage design methodology is presented and applied to an add-compare-select (ACS) unit, resulting in an eight-fold improvement in energy dissipation over similar designs. Simulations show that forward body-biased pseudo-NMOS logic yields superior power-delay product (PDP) over both static CMOS and transmission gate logic for high-performance systems at ultra-low voltages. A modified logic topology termed pseudo-pass transistor logic is used in conjunction with pseudo-NMOS to further reduce energy dissipation. At 500 mV, the ACS achieves a PDP of 0.6 pJ at 200 MHz.