A Power-Gating Technique for Adiabatic Circuits Using Bootstrapped NMOS Switches

This paper presents a power-gating technique for low-power adiabatic circuits. NMOS switches are used to detach adiabatic logic blocks from power-clocks. A NMOS bootstrapping scheme is presented, which are used to reduce turn-on resistors and energy overhead of NMOS switches. The PAL-2N (Pass-transistor adiabatic logic with NMOS pull-down configuration) circuits are investigated using the proposed power-gating technique and TSMC 0.18¿m CMOS process. SPICE simulations show that energy loss is reduced greatly by shutting down idle adiabatic circuit blocks. The proposed power-gating technique is suitable for the adiabatic units during idle periods to reduce dynamic power.