A New CMOS Current Integrating Receiver For GByte/s Parallel Links

A new fully differential current-integrating receiver for high-speed parallel links is proposed. The receiver consists of a transimpedance front-end stage and a sense amplifier-latch stage. The transimpedance front-end stage provides a low and tunable matching impedance to the channels. The sense amplifier with self-biased shunt-peaking active inductors significantly decreases the setup-hold of the sense amplifier and enables it to be used for high-speed application. The proposed receiver has been implemented in UMC 0.13¿m, 1.2V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3.3V device models. Simulation results have confirmed that the proposed current-integrating receiver provides full output voltage swing when the data rate is 2.5 Gbyte/s.