The Morphable Nanoprocessor Architecture: Reconfiguration at Runtime

Nanoprocessor architectures enable reconfiguration to optimize the hardware for a target appliction. Previous research proposes fixing the nanoprocessor configuration at compile time [10], [6], [13]. Runtime reconfiguration enables a nanoprocessor architecture to "learn" a more optimal way to use computational and memory resources in a changing computational environment. We propose two methods to reconfigure the nanoprocessor architecture at runtime: dynamic prefetching and dynamic simultaneous multi-threading. The dynamic prefetching engine optimizes its performance and resource utilization by changing its configuration. Dynamic simultaneous multithreading varies the number of concurrently running threads to optimize the tradeoff between thread-level and instruction-level parallelism.