A Comparison Between Noise-Immunity Design Techniques for Dynamic Logic Gates

Author

Gonzalez-Diaz, O. ; Linares-Aranda, M. ; Mendoza-Hernandez, F.

Author_Institution

Nat. Inst. for Astrophys., Opt. & Electron., Puebla

Volume

1

fYear

2006

fDate

6-9 Aug. 2006

Firstpage

484

Lastpage

488

Abstract

In this work, we analyze three design techniques to enhance the noise immunity of dynamic logic gates. A comparison in Power Consumption, Average Noise Threshold Energy (ANTE) and ANTE- normalized energy (EANTE) between the three techniques is presented. The dynamic logic gates using noise immunity techniques were designed with 0.35 mum, 0.18 mum, and 0.09 mum CMOS process technologies and power supply of 3.3 V, 1.8 V, and 1.0 V respectively. The obtained results show that for all technologies used in the simulations the Transparency Window technique [1] presents the best trade-off among noise immunity and performance as technology scales.

Keywords

CMOS logic circuits; integrated circuit noise; logic gates; CMOS process technologies; dynamic logic gates; noise-immunity design techniques; CMOS logic circuits; CMOS technology; Circuit noise; Crosstalk; Energy consumption; Logic circuits; Logic design; Logic gates; Optical noise; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on

Conference_Location

San Juan

ISSN

1548-3746

Print_ISBN

1-4244-0172-0

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2006.382104

Filename

4267181