Test Generation and Site of Fault for Combinational Circuits Using Logic Petri Nets

In this paper, we propose a novel Petri net model for solving test generation and site of fault and fired logical value for combinational circuits. In order to improve the logic fault efficiency, the transitions of general Petri nets (PNs) are modified according to the critical of truth table, called logic Petri net LPN. The LPN model can transfer complexity circuit problem to a local adjacent place and transition relational problem. Therefore, the site of fault and fired logical value problem is simplified and clearly. The LPN model has the properties of Boolean algorithm, collapsing fault with clear physical concepts, fast calculation speed, and high veracity. The approach contains site of a fault and fired logical value reasoning algorithm and test vector generation reasoning algorithm. Two examples are shown to demonstrate the effectiveness of our approach.