• DocumentCode
    466430
  • Title

    Phase guided sampling for efficient parallel application simulation

  • Author

    Namkung, Jeffrey ; Kim, Dohyung ; Gupta, Rajesh ; Kozintsev, Igor ; Bouget, Jean-Yves ; Dulong, Carole

  • Author_Institution
    Univ. of California, San Diego
  • fYear
    2006
  • fDate
    22-25 Oct. 2006
  • Firstpage
    187
  • Lastpage
    192
  • Abstract
    Simulating chip-multiprocessor systems (CMP) can take a long time. For single-threaded workloads, earlier work has shown the utility of phase analysis, that is identification of repetitive program behaviors, in reducing overall simulation time while maintaining an acceptable loss in accuracy. To cope with multithreaded workloads, a combination of phases from all executing threads must be taken into consideration since inter-thread interference may distort the homogeneity of each phases´ true performance. Unfortunately, phase analysis does not work for multithreaded (MT) workloads because the possible phase combinations in an inherently nondeterministic execution model grows exponentially with the number of threads. To this end, we propose a new technique to reduce the number of simulation samples by synthesizing samples from similar phase combinations. We present a simple cost function for measuring the similarity between phase combinations and by using the individual thread samples from the similar phase combinations, a new sample can be constructed. This cost function provides a convenient control knob for exploiting tradeoffs between simulation speed and accuracy. Our experimental results show that in most cases, properly setting the cost function´s threshold can yield a reduction in sampling by 90%, while maintaining error to less than 5%.
  • Keywords
    microprocessor chips; sampling methods; chip-multiprocessor system simulation; multithreading; parallel application simulation; phase guided sampling; Analytical models; Cost function; Interference; Multithreading; Performance analysis; Permission; Phase measurement; Sampling methods; Surface-mount technology; Yarn; chip multiprocessors; multithreading; phase analysis; sampling; simulation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Hardware/Software Codesign and System Synthesis, 2006. CODES+ISSS '06. Proceedings of the 4th International Conference
  • Conference_Location
    Seoul
  • Print_ISBN
    1-59593-370-0
  • Electronic_ISBN
    1-59593-370-0
  • Type

    conf

  • DOI
    10.1145/1176254.1176301
  • Filename
    4278513