DocumentCode
4666
Title
Voltage balancing technique in a space vector modulated 5-level multiple-pole multilevel diode clamped inverter
Author
Raj, Pinkymol Harikrishna ; Maswood, Ali I. ; Ooi, Gabriel H. P. ; Ziyou Lim
Author_Institution
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore
Volume
8
Issue
7
fYear
2015
fDate
7 2015
Firstpage
1263
Lastpage
1272
Abstract
Unbalanced voltage across the dc-link capacitors of classical diode clamped multilevel inverters (DCMI) generates lower order harmonics in the output voltage and increases the voltage stress on the switching devices which may result in permanent damage to the switching devices. This study proposes a space vector modulation (SVM) based voltage balancing strategy for a new 5-level multiple-pole multilevel diode-clamped inverter (M2DCI) topology to eliminate the voltage drift phenomena. The 5-level M2DCI topology which is derived from 3-level DCMI topology uses lesser number of clamping diodes compared with the conventional 5-level DCMI topology. An effective switching function model of a new multilevel inverter is derived and is used for dc-link capacitor voltage control. The method utilises the redundant vector property to balance the dc-link capacitor voltages without using any auxiliary hardware. The dependence of the capacitor voltage variation on the load power factor and modulation index has been extensively studied for 5-level M2DCI. The range of operation for the new topology with the proposed control strategy is also presented based on the simulation studies in the Matlab/Simulink® and PSIM environment and verified using experimental results.
Keywords
invertors; power capacitors; power factor; voltage control; 3-level DCMI topology; M2DCI topology; Matlab-Simulink; PSIM environment; SVM 5-level multiple-pole multilevel diode clamped inverter; capacitor voltage variation; dc-link capacitor voltage control; load power factor; modulation index; space vector modulation; switching devices; switching function model; voltage balancing technique; voltage drift phenomena; voltage stress;
fLanguage
English
Journal_Title
Power Electronics, IET
Publisher
iet
ISSN
1755-4535
Type
jour
DOI
10.1049/iet-pel.2014.0747
Filename
7150485
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