Title :
A 2-Mask NMOS Process Design Fabricate and Test Module for Use In Microelectronics Instruction and Process Development
Author_Institution :
San Jose State Univ., San Jose
Abstract :
We have developed a simplified 2-mask n-type metal oxide semiconductor (NMOS) transistor process design and verification module for electrical engineering students enrolled in the Microelectronic Manufacturing Methods class/laboratory at San Jose State University. We have run this module for three years and have found that the simplified process allows the students to learn more because they have the time to design the process fabricate and test in one semester. Student learning is also enhanced because it allows students to make and correct mistakes in the processing the devices. We have also found that the simplified process saves time in process development of more complex processes, by reducing the number of photolithography steps required to fabricate a transistor.
Keywords :
MOS integrated circuits; MOSFET; electronic engineering education; masks; photolithography; semiconductor device testing; semiconductor process modelling; 2-mask NMOS process design; San Jose State University; electrical engineering students; metal oxide semiconductor transistor process design; microelectronic manufacturing methods class/laboratory; microelectronics instruction; photolithography; process development; semiconductor process development; student learning; CMOS process; Circuit synthesis; MOS devices; Microelectronics; Physics; Process design; Semiconductor device manufacture; Semiconductor materials; Testing; Windows;
Conference_Titel :
University/Government/Industry Microelectronics Symposium, 2006 16th Biennial
Conference_Location :
San Jose, CA
Print_ISBN :
1-4244-0267-0
DOI :
10.1109/UGIM.2006.4286353
