Modeling Process Impact on Cu/Low k Interconnect Performance and Reliability

This paper studies the impact of layout alteration and structural variation on capacitance and spatial variations of electric and thermal mismatch stress fields. The fabrication process related layout alteration and structural variation include floating dummy fill insertions, silicon nitride cap layers thickness selections, and metal line cross-section shape changes. It is demonstrated that the spatial distributions of electric field and thermal-mechanical stress field have different geometric dependence and process variations have different implications. The layout pattern and interconnect architecture that are optimized for electric performance may be inferior in reliability due to large stress concentrations. The numerical results suggest that in pursuit of manufacturability the tradeoffs between electrical performance and mechanical reliability need to be considered together for future interconnect architecture and process technology developments.