Impact of Millisecond Anneals on CMOS Scaling - A Device Simulation Study

With the rapid scaling of CMOS devices towards the nanoscale regime as facilitated by lithography and strain engineering, the impact of parasitic series resistance is becoming a bigger issue. The need for shallower junctions to meet the short channel control requirements of the scaled transistors also aggravates the series resistance problem. Advanced technologies like millisecond laser anneal, which produce abrupt, highly activated junctions with negligible diffusion, are being proposed to meet junction requirements of 45 nm technology node and beyond. But integrating the millisecond anneals into an existing spike baseline CMOS flow has not yet been fruitful. The increased overlap resistance due to the lack of lateral diffusion in the case of millisecond anneals is considered to offset the benefits of the otherwise abrupt and highly activated junctions. Thus for successful implementation of these advanced anneal technologies it is essential to understand the relative contributions of different components of series resistance and how it is impacted by the different USJ parameters like gate-source/drain overlap, lateral abruptness, junction depth and peak active doping concentration.