Title :
6 Bit Decimation Filter in Sub-threshold Region
Author :
Jain, Ritu ; Guttal, Pratibha ; Parent, D.W.
Author_Institution :
San Jose State Univ., San Jose
Abstract :
We show the design of a 6-bit decimation filter with a decimation factor 4 operating in sub threshold region. We find that the optimum Wp/Wn ratio for an inverter operating in the sub-threshold was 24 as measure by equalizing NMOS and PMOS transistors drives. At the maximum achievable operating frequency of 50 kHz the circuit uses 2.5 nW of power and occupies an area of 47 mum times 100 mum. TSMC 0.18 mum technology, with a supply voltage of 300 mV was used.
Keywords :
digital filters; field effect digital integrated circuits; NMOS transistors drives; PMOS transistors drives; TSMC; digital sub threshold region decimation filter; power 2.5 nW; size 0.18 mum; voltage 300 mV; word length 6 bit; Circuits; Energy consumption; Filters; Frequency; Inverters; Leakage current; MOS devices; Sampling methods; Threshold current; Threshold voltage; CMOS; Low Power; Subthreshold;
Conference_Titel :
University/Government/Industry Microelectronics Symposium, 2006 16th Biennial
Conference_Location :
San Jose, CA
Print_ISBN :
1-4244-0267-0
DOI :
10.1109/UGIM.2006.4286385
