Minimum Communication Cost Approaches for Dynamically Reconfigurable FPGA

The FPGA-based configurable computing machines are evolving rapidly, due to their flexibility and high performance. The communication cost is one of important factors in dynamically reconflgurable FPGA. This paper proposes a scheduling technique based on network flow partitioning for the dynamically reconfigurable FPGA to reduce communication cost. We use a scheduling technique in which gate can not be replicated to minimize the communication cost. By constructing a graph the scheduling technique is converted to minimize communication cost. This algorithm was tested on a set of benchmark examples. The experimental results demonstrate effectiveness of this proposed algorithm.