FPGA Implementation of Gated Clock based Globally Asynchronous Locally Synchronous Wrapper Circuits

This paper focuses on prototyping pausible and gated clock based GALS systems on commercial FPGAs. Pausible clock based GLAS systems use an on-chip clock generator to generate pausible clock pulses whereas gated clock based GALS systems use an off-chip clock signal that is gated whenever asynchronous data communication is required. These two design schemes have been examined on Viterbi error detection and correction circuit. While using on-chip pausible clocks in plausible GALS wrappers leads to a tradeoff between robustness and performance, it has been shown that both performance and robustness can be improved by using the gated clock scheme. In addition, the area overhead of gated clock based GALS Viterbi was less than the area overhead of pausible clock based GALS Viterbi.