DocumentCode
467547
Title
On-Die Interconnect and Other Challenges for Chip-Level Multi-Processing
Author
Fossum, Tryggve
Author_Institution
INTEL Corp., Santa Clara
fYear
2007
fDate
22-24 Aug. 2007
Firstpage
4
Lastpage
4
Abstract
There is increasing interest in chip-level multi-processing, and in this talk I will discuss some the motivations, and some of the challenges in designing such chips. A key component is the on-die interconnect, and we will look at this along with some thoughts on core design, cache architecture, memory bandwidth, power management, error handling, and system scaling.
Keywords
integrated circuit design; integrated circuit interconnections; cache architecture; chip-level multiprocessing; core design; error handling; memory bandwidth; on-die interconnect; power management; system scaling; Bandwidth; Computer errors; Design engineering; Energy management; Memory architecture; Memory management; Microarchitecture; Microprocessors; Power system interconnection; Power system management;
fLanguage
English
Publisher
ieee
Conference_Titel
High-Performance Interconnects, 2007. HOTI 2007. 15th Annual IEEE Symposium on
Conference_Location
Stanford, CA
ISSN
1550-4794
Print_ISBN
978-0-7695-2979-0
Type
conf
DOI
10.1109/HOTI.2007.29
Filename
4296799
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