Abstract :
There is increasing interest in chip-level multi-processing, and in this talk I will discuss some the motivations, and some of the challenges in designing such chips. A key component is the on-die interconnect, and we will look at this along with some thoughts on core design, cache architecture, memory bandwidth, power management, error handling, and system scaling.
Keywords :
integrated circuit design; integrated circuit interconnections; cache architecture; chip-level multiprocessing; core design; error handling; memory bandwidth; on-die interconnect; power management; system scaling; Bandwidth; Computer errors; Design engineering; Energy management; Memory architecture; Memory management; Microarchitecture; Microprocessors; Power system interconnection; Power system management;
