Timing- / Power-Optimization for Digital Logic Based on Standard Cells

Physical design for digital ICs, based on standard cells, has long been performed without explicit consideration of timing and power related to interconnects. With delays on wires more and more dominating the delays on logic paths, such design styles are becoming obsolete. What is needed is an iterative inclusion of power and timing aspects into the design flow for placement and routing, which yields economic results without multiple loops in the design flow. Basic problems and solutions in the implementation of such a design flow are presented.