• DocumentCode
    467614
  • Title

    Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration

  • Author

    Paul, Kolin ; Porquet, Joel

  • Author_Institution
    Dept. of Comput. Sci., IIT Delhi, New Delhi, India
  • fYear
    2007
  • fDate
    29-31 Aug. 2007
  • Firstpage
    317
  • Lastpage
    324
  • Abstract
    The effective use of Run Time Reconfiguration (RTR) in modern FPGAs opens up new avenues to design area and power efficient high performance architectures. However the current design flow for exploiting RTR in designs, leads to the problem of silicon Defragmentation. We propose a silicon compaction/defragmentation technique which works on already placed and routed modules to generate partial bitstreams (programming files) for the device. We have outlined a method which generates these partial bitstreams very fast taking into account the size and position of the "free" silicon when the device is in operation. The other advantage of this method is that the changes in the basic FPGA fabric needed to implement this defragmentation strategy are (almost) trivial.
  • Keywords
    field programmable gate arrays; FPGA; high performance architecture; partial bitstreams; partial runtime reconfiguration; programming files; silicon compaction; silicon defragmentation; Circuits; Compaction; Computer science; Fabrics; Field programmable gate arrays; Process design; Programming profession; Runtime; Silicon; Virtual manufacturing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on
  • Conference_Location
    Lubeck
  • Print_ISBN
    978-0-7695-2978-3
  • Type

    conf

  • DOI
    10.1109/DSD.2007.4341487
  • Filename
    4341487