MPSoC memory optimization for digital camera applications

Multiprocessor system-on-a-chip architectures have received a lot of attention in the past years, but few advances in compilation techniques are targeting these architectures. This is particularly true for the exploitation of data locality. Most of the compilation techniques discussed in the literature for parallel architectures are based on single loop nest. However, most multimedia and image processing applications are composed of several loop nests. In this paper, new techniques based on program transformations are proposed to optimize these types of applications. In a monoprocessor architecture, the loop fusion technique is well known. In this paper, the loop fusion is generalized and adapted to a MPSoC architecture. Another technique called "computation propagation " is proposed. It completely removes the temporary arrays and significantly reduces the memory accesses, the memory space and the processing time. Experimental results show that this new technique yields a significant reduction in the number of data cache misses (35%), in processing time (30%) and in channel transactions (85%).