DocumentCode
468038
Title
Silicic Compiling as Instrument of Planning of Topology of Large-Scale Arrays and Providing its Reliability at Algorithmic Level
Author
Atamanyuk, R.B. ; Novosiadly, S.P.
Author_Institution
Nat. Univ., Ivano-Francovsk
fYear
2006
fDate
Feb. 28 2006-March 4 2006
Firstpage
604
Lastpage
605
Abstract
In this paper the advantages of the method of silicon compilation are described. Proposed the time -probability kriterion for minimization of algoritmical processes by silicon compilation.
Keywords
circuit layout CAD; circuit reliability; minimisation; network topology; algorithmic level; algorithmical processes; large-scale arrays; minimization; reliability; silicic compiling; silicon compilation; time-probability criterion; topology; Aggregates; Algorithm design and analysis; Circuit topology; Error correction; Instruments; Large-scale systems; Matrix decomposition; Minimization; Program processors; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Modern Problems of Radio Engineering, Telecommunications, and Computer Science, 2006. TCSET 2006. International Conference
Conference_Location
Lviv-Slavsko
Print_ISBN
966-553-507-2
Type
conf
DOI
10.1109/TCSET.2006.4404650
Filename
4404650
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