CPU Package Design Optimization for Performance Improvement and Package Cost reduction

Author

Howe Yin Loo ; Boon Howe Oh ; Poh Tat Oh ; Eng Kwong Lee

Author_Institution

Intel Microelectron. Sdn Bhd, Penang

fYear

2006

fDate

11-14 Dec. 2006

Firstpage

1

Lastpage

5

Abstract

CPU packages continue to undergo significant changes to keep pace with demands of high performance silicon to meet market needs. In the last decades or so, increasingly CPU performance and frequency levels couples with lower product cost have been driving new package technologies. This paper illustrates an approach in CPU package design optimization for performance improvement and package cost reduction through effective capacitor usage and package layer count reduction. This involves the new proposed package stack-up designed to lower packaging cost and as well as mixed type capacitor usage in package power delivery.

Keywords

capacitors; cost reduction; design engineering; electronics packaging; optimisation; CPU package design optimization; effective capacitor; high performance silicon; mixed type capacitor; package cost reduction; package layer count reduction; package power delivery; Capacitors; Cost function; Design optimization; Frequency; Impedance; Inductance; Packaging; Silicon; Space heating; Technological innovation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Materials and Packaging, 2006. EMAP 2006. International Conference on

Conference_Location

Kowloon

Print_ISBN

978-1-4244-0834-4

Electronic_ISBN

978-1-4244-0834-4

Type

conf

DOI

10.1109/EMAP.2006.4430591

Filename

4430591