Package Routing and Thermal Analysis on a Multi-Chip Package (MCP)

Author

Boon Howe Oh ; Eng Kwong Lee ; Howe Yin Loo ; Poh Tat Oh

Author_Institution

Bayan Lepas FTZ, Penang

fYear

2006

fDate

11-14 Dec. 2006

Firstpage

1

Lastpage

5

Abstract

In today conventional technology, multi-chip packaging (MCP) technology has become more important and popular with the purpose to increase the density of the integrated electronic and processing power. However, increasing in processing speed and enhanced capabilities for high power chip design, thermal management in MCP has become more challenging in heat dissipation due to multiple heat sources. This paper presents the package layout design optimization which plays an important role in ensuring multi chip assembly design rules are met and several approaches to optimize the placement of two dice in a single package will be presented. This paper also illustrates the overview of thermal analysis in MCP to study the effect of balanced and unbalanced power map to the thermal solution of MCP in relation to junction temperature.

Keywords

chip scale packaging; cooling; integrated circuit design; integrated circuit layout; multichip modules; thermal analysis; thermal management (packaging); heat dissipation; high power chip design; integrated electronics; junction temperature; multi chip assembly design rules; multichip packaging technology; multiple heat source; package layout design optimization; package routing; thermal analysis; thermal management; Assembly; Design optimization; Electronic packaging thermal management; Energy management; Heat sinks; Heat transfer; Resistance heating; Routing; Temperature; Thermal management;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Materials and Packaging, 2006. EMAP 2006. International Conference on

Conference_Location

Kowloon

Print_ISBN

978-1-4244-0834-4

Electronic_ISBN

978-1-4244-0834-4

Type

conf

DOI

10.1109/EMAP.2006.4430592

Filename

4430592