Title :
A CCD clock controller ASIC using novel design techniques integrated in a CMOS 0.8μm SOI high voltage process
Author :
Walder, J.P. ; Abiad, R. ; Bebek, C.J. ; Chao, G. ; Gnani, D. ; Karcher, A. ; Krieger, B. ; von der Lippe, H.
Author_Institution :
Lawrence Berkeley Nat. Lab., Berkeley
fDate :
Oct. 26 2007-Nov. 3 2007
Abstract :
An ASIC designed to provide the clock signals to the focal plane CCDs for the SNAP satellite project is presented. A prototype has been implemented in a CMOS 0.8 mum SOI high voltage process in order to accommodate a 20 V output swing. The circuit consists of a main charge pump multiplying the 4 V power supply voltage +/-16 V followed by a controlled current source setting the clock voltage plateaus. A bridge of switches provides the clock voltage transitions at the output. This circuit is designed to operate at room temperature for test purpose and at 140 K, which will be the operating temperature. Novel design techniques used in this chip will be presented in detail along with measurement results obtained on the prototypes.
Keywords :
CMOS integrated circuits; application specific integrated circuits; charge-coupled devices; clocks; integrated circuit design; prototypes; silicon-on-insulator; CCD clock controller; CMOS SOI high voltage process; SNAP satellite project; clock voltage plateaus; clock voltage transitions; controlled current source; main charge pump; power supply; prototypes; room temperature; size 0.8 mum; temperature 140 K; temperature 293 K to 298 K; voltage 20 V; Application specific integrated circuits; CMOS process; Charge coupled devices; Circuit testing; Clocks; Process design; Prototypes; Signal design; Temperature; Voltage control;
Conference_Titel :
Nuclear Science Symposium Conference Record, 2007. NSS '07. IEEE
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-0922-8
Electronic_ISBN :
1095-7863
DOI :
10.1109/NSSMIC.2007.4436627
