Title :
Hierarchical Test Integration Methodology for 3-D ICs
Author :
Che-Wei Chou ; Jin-Fu Li ; Yun-Chao Yu ; Chih-Yen Lo ; Ding-Ming Kwai ; Yung-Fa Chou
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Taoyuan, Taiwan
Abstract :
In this paper, we propose a hierarchical test integration method for 3-D ICs. The method can handle a die with logic cores and memory cores. In addition to handle the test controlling of a hierarchical 3-D IC, furthermore, it also can support the test controlling of a 3-D IC with multiple towers. For a 3-D IC, the hierarchical test integration method uses two types of 1149.1-based test interfaces for the bottom die and nonbottom dies. Therefore, the test access ports for the two test interfaces are the same. Also, the number of required test pads of the proposed test interface is only 4. Furthermore, the test interface is compatible with the IEEE 1149.1 standard for the board-level testing.
Keywords :
IEEE standards; integrated circuit testing; integrated memory circuits; logic circuits; logic testing; three-dimensional integrated circuits; IEEE 1149.1 standard; board-level testing; herarchical test integration methodology; hierarchical 3D IC; logic cores; memory cores; nonbottom dies; test access ports; test controlling; test interfaces; three-dimensional integrated circuits; Built-in self-test; Discrete Fourier transforms; Integrated circuits; Registers; Switches; Three-dimensional displays; 3D IC; BIST; hierarchical test; test interface; through-silicon-via (TSV);
Journal_Title :
Design & Test, IEEE
DOI :
10.1109/MDAT.2015.2427257
