At-Speed SEE Testing of RHBD Embedded SRAMs

Author

Cannon, E.H. ; Tostenrude, J. ; Cabanas-Holmen, M. ; Meaker, Barry ; Neathery, Charles ; Carson, Mike ; Brees, R.

Author_Institution

Boeing Co., Seattle, WA, USA

Volume

60

Issue

6

fYear

2013

fDate

Dec. 2013

Firstpage

4207

Lastpage

4213

Abstract

We describe a test structure architecture that allows at-speed Single Event Effects (SEE) testing on embedded memory arrays. The at-speed test structure enables identification of Multiple Cell Upsets (MCU), Multiple Bit Upsets (MBU), persistent errors and transient errors. Error Detection and Correction (EDAC) can reduce the residual error rate due to SEU by multiple orders of magnitude. Consequently, careful testing of the at-speed test structure is essential to detect and quantify the risk of rare, uncorrectable MBU.

Keywords

SRAM chips; error correction; error detection; radiation hardening (electronics); transients; RHBD embedded SRAM; at-speed SEE testing; at-speed single event effects testing; embedded memory arrays; error detection and correction; multiple bit upsets; multiple cell upsets; persistent errors; residual error rate; test structure architecture; transient errors; Error analysis; Radiation effects; Radiation hardening (electronics); SRAM chips; Single event transients; Single event upsets; Heavy ion radiation effects; SRAM; multiple bit upset; multiple cell upset; radiation effects; single event transient; single event upset; single-event effects;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2013.2288307

Filename

6677617