Title :
A High Performance CMOS Process with Half-Micron Gate and Novel Low-Parasitic Salicide Interconnect Scheme
Author :
Lau, C.K. ; Cham, K.M. ; Liu, D. ; Wenocur, D.W. ; Chen, D.C. ; Fu, H.S.
Author_Institution :
Hewlett-Packard Laboratories 3500 Deer Creek Road, Palo Alto, California 94304
Keywords :
CMOS process; Capacitance; Delay; Fabrication; Geometry; Integrated circuit interconnections; Lithography; Power dissipation; Ring oscillators; Silicides;
Conference_Titel :
VLSI Technology, 1985. Digest of Technical Papers. Symposium on
Conference_Location :
Kobe, Japan
Print_ISBN :
4-930813-09-3
