Modeling of Hot Carrier Effects for LDD MOSFETs

In the strive for faster and more complex integrated circuits, the device geometries and minimum feature size have been scaled down aggressively to achieve the desired circuit performance. The resulting high electric fields favor the generation and injection of hot carriers near the drain in MOS devices[1-3]. Both threshold voltage(Vt) shift and transconductance(gm) degradation have been reported by many researchers[4-8]. For LDD devices, only gm degradation was reported and was believed to be either caused by mobility degradation due to interface-state generation[6,7] or by localized charge [8]. One objective of our work is to show that for LDD devices in addition to gm degradation, Vt shift and variations for all short channel SPICE model parameters are observed. There are also good correlations between the variations of those short channel parameters. The other objective is to identify the degradation mechanisms by theoretical modeling, simulation, and experimental results. Our modeling results indicate that localized charge or mobility degradation alone can not explain the observed experimental results. A spatial charge distribution model was identified to predict the experimental results.