Title :
A New CMOS SRAM Cell with Fully Planarizing Technology
Author :
Narita, Yoshitaka ; Ohya, Shuichi ; Kikuchi, Masanori
Author_Institution :
1st LSI Division, NEC Corporation 1120, Shimokuzawa, Sagamihara, Kanagawa 229, Japan
Keywords :
CMOS technology; Etching; Filling; Flip-flops; Large scale integration; National electric code; Planarization; Random access memory; Resists; Surface morphology;
Conference_Titel :
VLSI Technology, 1987. Digest of Technical Papers. Symposium on
Conference_Location :
Karuizawa, Japan
