DocumentCode :
472772
Title :
0.5μm CMOS Technology for 5.6nsec High Speed 16x16 Bit Multiplier
Author :
Tsuda, Kazusui ; Takato, Hiroshi ; Takenouchi, Naoko ; Tsuchiya, Kenji ; Oowaki, Yukihito ; Nukata, Kenji ; Nitayama, Akihiro
Author_Institution :
VLSI Research Center, Toshiba Corporation 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki 210, Japan
fYear :
1987
fDate :
22-23 May 1987
Firstpage :
109
Lastpage :
110
Abstract :
CMOS technology becomes indispensable for designing VLSI circuits because of high speed, wide noise margin, and low power dissipation. Moreover, scaled down half a micron CMOS circuits have a large impact on high speed operation, where the speed is comparable to that of bipolar and GaAs. However, when CMIOS devices are scaled down to half micron, it is difficult to suppress punchthrough and parasitic resistance for PMOSFETs and hot carrier degradation for NMOSFETs.
Keywords :
CMOS technology; Circuit noise; Degradation; Gallium arsenide; Hot carriers; MOSFETs; Parasitic capacitance; Power dissipation; Very large scale integration; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, 1987. Digest of Technical Papers. Symposium on
Conference_Location :
Karuizawa, Japan
Type :
conf
Filename :
4480446
Link To Document :
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