1 μm Mo Gate MOS Technology

A process technology for the high performance 1 μm Mo gate NMOS devices with MNOS and Si₃N₄+CVD SiO₂ passivation structure has been demonstrated in this paper. The features of this technology are summarized as follow: 1) Contamination by mobile ions is blocked by a double-layer gate insulator and double-layer passivation of 20-nm Si₃N₄ film. MOSFET with little fluctuation in electrical characteristics is fabricated. 2) There arises no limitation to the process flexibility. 3) An inverter stage in a ring oscillator is switched as fast as 150 ps with less than 14 fJ power-delay product. At smaller V_DD, even faster operations are realized. This 1 μm Mo gate process technology will allow high-speed and high-density VLSIs.