472826

A CMOS Pair-Transistor Array Masterslice

Fukuda, Hideki ; Yoshimura, Hiroshi ; Adachi, Tohru

Musashino Electrical Communication Laboratory, NTT Musashino-shi, Tokyo, Japan

1982

1-3 Sept. 1982

16

17

CMOS logic circuits; Integrated circuit interconnections; Laboratories; Large scale integration; Logic functions; Random access memory; Read only memory; Routing; Very large scale integration; Wiring;

English

ieee

VLSI Technology, 1982. Digest of Technical Papers. Symposium on

Oiso, Japan

conf

4480557