DocumentCode
472843
Title
Power-Up Triggering Conditions for Latch-Up in Bulk CMOS
Author
Troutman, R.R. ; Zappe, H.P.
Author_Institution
IBM General Technology Division Essex Junction, Vermont 05452
fYear
1982
fDate
1-3 Sept. 1982
Firstpage
52
Lastpage
53
Keywords
Analytical models; CMOS integrated circuits; CMOS technology; Capacitance; Integrated circuit technology; Knee; Piecewise linear approximation; Resistors; Transient analysis; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1982. Digest of Technical Papers. Symposium on
Conference_Location
Oiso, Japan
Type
conf
Filename
4480574
Link To Document