• DocumentCode
    472847
  • Title

    Topography Dependent Step Coverage Resistance Simulation for VLSI Design

  • Author

    Lee, Keunmyung ; Sakai, Yoshio ; Neureuthe, Andrew R.

  • Author_Institution
    EECS and ERL, University of California, Berkeley Berkeley, California 94720, U.S.A.
  • fYear
    1982
  • fDate
    1-3 Sept. 1982
  • Firstpage
    60
  • Lastpage
    61
  • Keywords
    Capacitance; Circuit optimization; Circuit simulation; Electric resistance; Integrated circuit interconnections; Laplace equations; Shape measurement; Sputtering; Surface resistance; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, 1982. Digest of Technical Papers. Symposium on
  • Conference_Location
    Oiso, Japan
  • Type

    conf

  • Filename
    4480578
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=472847