Title :
Topography Dependent Step Coverage Resistance Simulation for VLSI Design
Author :
Lee, Keunmyung ; Sakai, Yoshio ; Neureuthe, Andrew R.
Author_Institution :
EECS and ERL, University of California, Berkeley Berkeley, California 94720, U.S.A.
Keywords :
Capacitance; Circuit optimization; Circuit simulation; Electric resistance; Integrated circuit interconnections; Laplace equations; Shape measurement; Sputtering; Surface resistance; Very large scale integration;
Conference_Titel :
VLSI Technology, 1982. Digest of Technical Papers. Symposium on
Conference_Location :
Oiso, Japan
